1. Field of the Invention
The present disclosure generally relates to digital communications and, more particularly, to resolving clock time between asynchronous time domains.
2. Description of the Related Art
Often, digital devices communicate and transfer data across differing clock domain boundaries. Signals or data crossing these different clock time domain boundaries can develop errors if not properly synchronized.
In conventional clock and data synchronization systems, handshake circuits and synchronizers are used to facilitate such data transfers and resolve asynchronous transfer related timing issues. Typically, flip-flops or FIFO elements are used, which can hold data from one clock domain, i.e. the load value constant or stable until the other, asynchronous clock domain can sample the data, typically under controlled sampling point. However, holding data constant or stable can typically lead to slower system response times and/or it may impact the accuracy of the transfers in particular, if the destination is running at a comparable or slower clock speed with respect to the source. In the aggregate, this leads to an overall slower or reduced system performance.
Although the conventional techniques such as handshake circuits and synchronizers have generally been considered satisfactory for their intended purpose, there is still a need in the art for improved techniques that accurately and efficiently resolve cyclic and recurring data transfers such as, clock times between asynchronous time domains.